Samsung presented three next-generation memory technologies at the Future of Memory and Storage (FMS) 2026 conference, each designed to address critical bottlenecks in artificial intelligence data centers. The new architectures zHBM, zNAND-O and BV-NAND share a common manufacturing breakthrough: advanced wafer bonding that stacks memory directly onto logic circuits, dramatically reducing data travel distances.

What You Need to Know

These technologies represent a shift toward integrating memory with processing logic rather than placing them on separate silicon. Samsung's approach mirrors industry trends seen at competitors like Kioxia and Sandisk, which also use bonding to improve NAND performance. For AI workloads, this could mean higher bandwidth and lower power consumption in large-scale deployments. The announcement came alongside growing interest in custom HBM solutions for next-generation accelerators.

Wafer Bonding Unifies Three Memory Innovations

Samsung has previously relied on traditional interposer and packaging methods for high-bandwidth memory. The new designs bond memory arrays directly onto logic dies, eliminating physical distance between compute and storage. This technique, already used by Kioxia and Sandisk for some NAND products, lets Samsung pursue more aggressive performance targets. Analysts at Tom's Hardware Premium have noted that wafer bonding enables tighter integration that was previously considered too complex for volume production.

  • zHBM: Custom high-bandwidth memory stacked directly on top of an AI accelerator logic die instead of on its perimeter. Samsung claims this can deliver eight times the performance of HBM5.
  • zNAND-O: NAND memory bonded atop a logic device to maximize bandwidth, reduce latency and minimize power consumption for data-intensive workloads.
  • BV-NAND: Samsung's 10th Generation V-NAND that bonds NAND arrays directly above the control circuitry, echoing a method pioneered by YMTC and now adopted by nearly all NAND makers including Kioxia and Sandisk.

zHBM Targets AI Accelerator Bandwidth Limits

This memory architecture aims to solve a persistent challenge in AI hardware: moving data quickly enough between memory and processors. By placing HBM stacks directly over the accelerator, the distance signals must travel shrinks dramatically. Samsung projects that zHBM can achieve bandwidth and power efficiency improvements well beyond what HBM4 or even HBM5 can offer. The design, however, requires solving thermal and power delivery issues that have kept most manufacturers from implementing such vertical stacking at scale.

zNAND-O and BV-NAND Bring Bonding to Storage

While zHBM targets the highest tiers of AI memory, zNAND-O and BV-NAND focus on storage performance. zNAND-O bonds NAND directly to a logic chip, effectively creating a memory module with an integrated controller that reduces data path length. This technology borrows concepts from system-in-package designs and could appear in future AI storage nodes. BV-NAND, meanwhile, represents Samsung's evolution of 3D NAND itself: by bonding the memory array to the underlying peripheral circuits, the company can pack more layers and improve signal integrity. This is the same fundamental approach used in Kioxia and Sandisk's latest NAND generations.

Why This Matters

The implications extend beyond Samsung's product roadmap. For AI data center operators, these technologies promise to reduce the energy consumed by moving data between memory and compute, a major cost driver in large-scale training clusters. For the broader semiconductor industry, Samsung's commitment to wafer bonding signals that the technique has moved from experimental to production-ready. Competitors like Kioxia and Sandisk will need to accelerate their own bonding roadmaps to maintain parity. The ultimate winners are hyperscale cloud providers and AI startups that depend on ever-faster memory subsystems to keep GPU and accelerator utilization high.